1. Field of the Invention
The present invention relates to an active matrix circuit which is used for display with a liquid crystal, and other purposes.
2. Description of the Related Art
FIG. 6 schematically shows an example of a conventional active matrix display device. In a display area which is enclosed by a broken line in FIG. 6, transistors Tr as switching elements are arranged in matrix form such that a single transistor is provided for each matrix element. When attention is paid to an nth-row/mth-column element of the matrix, an image (data) signal line Ym is connected to the source of the transistor Tr and a gate (selection) signal line Xn is connected to the gate electrode of the transistor Tr.
Attention is now paid to the transistor as the switching element, which performs data switching and drives a liquid crystal cell LC. An auxiliary capacitor C, which supplements the capacitance of the liquid crystal cell LC, is used to hold image data. The transistor Tr switches image data, i.e., a voltage, to be applied to the liquid crystal. The most serious problem in using a transistor as s switching element is leak current (or off-current) that flows in a state that no selection pulse is applied to the gate (non-selection state). If the leak current is large, the amount of charge stored in the pixel electrode and the auxiliary capacitor easily decreases, resulting in deterioration in display performance.
An object of the invention is therefore to provide an active matrix circuit having small off-current.
According to the invention, a switching element is provided which is a series connection of a plurality of transistors. One end of the switching element is connected to a data signal line and the other end is connected to a pixel electrode. The respective transistors are controlled by independent gate signal lines. Connecting the transistors in series is effective in reducing the leak current.
More specifically, according to a first aspect of the invention, there is provided an active matrix circuit including first and second switching elements provided adjacent to each other and connected to the same data signal line and first to third gate (selection) signal lines that are adjacent to each other. The first switching element is controlled by the first and second gate signal lines while the second switching element is controlled by the second and third gate signal lines.
According to a second aspect of the invention, there is provided an active matrix circuit including first and second switching elements provided adjacent to each other and connected to the same data signal line and first to fourth gate (selection) signal lines that are adjacent to each other. The first switching element is controlled by the first and second gate signal lines while the second switching element is controlled by the third and fourth gate signal lines. The same signal is applied to the second and third selection signal lines.
FIGS. 1A and 1B are circuit diagrams showing the above-described first and second aspects of the invention, respectively. In these figures, a portion enclosed by a broken line corresponds to a pixel unit. In each of FIGS. 1A and 1B, each switching element consists of two transistors Tr1 and Tr2, which are controlled by different gate signal lines. In the case of FIG. 1B, two gate signal lines Xn and Zn are provided for each row. However, as shown in FIG. 1B, the gate signal line Zn and a gate signal line Xn+1 of the next row are connected to each other outside the matrix, and therefore supplied with the same signal.
In each of the first and second aspects of the invention, an auxiliary capacitor C may be provided as in the conventional case of FIG. 6. However, although in the conventional case a capacitor can be formed between the pixel electrode and the gate signal line Xn+1 adjacent thereto as shown in FIG. 7, such a configuration is not preferable in the invention. This is because in the invention the gate signal line adjacent to the pixel electrode is the one for driving the pixel concerned, and therefore in the above configuration the potential of the pixel electrode would vary (called a through voltage drop) in accordance with on/off switching of a selection pulse.
Therefore, in the invention, it is preferred that an auxiliary capacitor be formed between the pixel electrode and a wiring line other than the gate signal line. For example, a capacitor may be provided such that a light-shielding layer is formed with a conductive material so as to overlap with the pixel electrode and is kept at a constant potential. Alternatively, as shown in FIG. 1C, a capacitor may be provided by forming an overlap between an intermediate portion of the transistors Tr1 and Tr2 and the gate signal line for controlling the transistor Tr2. In this case, it is not preferable to provide a capacitor between the intermediate portion and the gate signal line for controlling the transistor Tr1 for a reason described later. In FIG. 1C, an auxiliary capacitor C is provided in the circuit of FIG. 1A. An auxiliary capacitor may also be provided in the circuit of FIG. 1B in a similar manner.
As is derived from the above discussion, in the first aspect of the invention, pulses applied to the first and second gate signal lines overlap in time with each other and, similarly, pulses applied to the second and third gate signal lines overlap in time with each other. If pulses applied to the first and second gate signal lines did not overlap in time with each other, the transistors Tr1 and Tr2 could not be turned on at the same time and hence the pixel electrode could not be charged.
Similarly, in the second aspect of the invention, pulses applied to the first and second gate signal lines overlap in time with each other and pulses applied to the third and fourth gate signal lines overlap in time with each other, in which the same pulse is applied to the second and third gate signal lines.
FIGS. 2A and 2B illustrate the above relationship. In FIGS. 2A and 2B, symbols Vn represents a voltage waveform of the gate signal line Xn in FIG. 1A and Dm represents a voltage waveform of the data signal line Ym. As seen from FIGS. 2A and 2B, pulses of Vn and Vn+1 overlap with each other and pulses of Vn+1 and Vn+2 overlap with each other, and a pulse of Dm in an overlapping period is written to the pixel electrode concerned; that is, a pulse D(Zn, m) is written to the pixel Zn,m and a pulse D(Zn+1, m) is written to the pixel Zn+1, m. For comparison, Vn is also shown on Vn+2 and Dm by a broken line.
FIG. 2A shows a case where selection pulses are sequentially applied to the gate signal lines from the top; in more general terms, a selection pulse is applied to the transistor Tr1 that is connected to the data signal line earlier than to the transistor Tr2 (the transistor Tr1 turns on or off earlier than the transistor Tr2). FIG. 2B shows a case where selection pulses are sequentially applied to the gate signal lines from the bottom; that is, a selection pulse is applied to the transistor Tr2 that is connected to the pixel electrode earlier than to the transistor Tr1 (the transistor Tr2 turns on or off earlier than the transistor Tr1). In the case of FIG. 2B, the data signal Dm may have a waveform of FIG. 2C.
Where a capacitor is formed between the intermediate portion of the transistors Tr1 and Tr2 and a particular gate signal line as shown in FIG. 1C, it should be taken into consideration that the capacitor does not work as an auxiliary capacitor in the operation mode where selection pulses are applied to the gate signal lines from the bottom.
For example, a consideration will be made of the operation mode of FIG. 2B. As for the pixel Zn, m, naturally data D(Zn, m) is written to this pixel in a state that both transistors Tr1 and Tr2 are on. Then, the transistor Tr2 is turned off while the transistor Tr1 is kept on, and the next data is applied to the data signal line. Naturally no variation occurs in the potential of the pixel capacitor LC because the transistor Tr2 is off. However, the next data is written to the capacitor C. Therefore, the capacitor C does not work as an auxiliary capacitor of the pixel capacitor LC. The same thing applies to the case of FIG. 2C.
In the invention, it is impossible to supplies data to the pixel concerned over the entire period when the transistor Tr1 is on, because the transistor Tr1 is involved in the signal control of the pixel of the above row.
From the above discussion, it will become apparent why it is not preferable to form a capacitor between the intermediate portion of the transistors Tr1 and Tr2 and the gate signal line Xn that controls the transistor Tr1 earlier. In such a circuit arrangement, to avoid a variation in the potential of the pixel electrode due to coupling of the capacitor C and the gate signal line, it is necessary to turn off the transistor Tr2 earlier, that is, to employ the operation mode where selection pulses are applied to the gate signal lines from the bottom. However, in such a case, the transistor Tr1 is kept on even after the transistor Tr2 is turned off, so that a signal not intended for the pixel concerned is written to the capacitor C. Thus, the capacitor C does not properly work as an auxiliary capacitor. Further, when the transistor Tr1 turns off, the potential of the capacitor C drops considerably, i.e., as much as the potential drop on the gate signal line. Forming the capacitor C in the above manner is not preferable also in this respect.
In the operation mode where selection pulses are applied to the gate signal lines from the top, the transistor Tr1 is turned off earlier and at this time point the potential of the capacitor C is equal to that of the pixel capacitor LC. Even if the transistor Tr2 is thereafter turned off, there occurs no problem because there is no current exchange with the data signal line any more.